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>INTRO.HTML Assembler: Chapter 1: Introduction >OBJASM.HTML Assembler: Chapter 2: ObjAsm >CPU.HTML Assembler: Chapter 3: The ARM CPU >ASMLANG.HTML Assembler: Chapter 4: ARM assembly language >INSTRSET.HTML Assembler: Chapter 5: CPU instruction set >FPINSTRS.HTML Assembler: Chapter 6: Floating point instructions >DIRECTIV.HTML Assembler: Chapter 7: Directives >SYMBOLIC.HTML Assembler: Chapter 8: Symbolic capabilities >EXPROP.HTML Assembler: Chapter 9: Expressions and operators >CONDASM.HTML Assembler: Chapter 10: Conditional assembly >MACROS.HTML Assembler: Chapter 11: Macros >EXHANDLE.HTML Assembler: Chapter 12: Exception handling >WRITERM.HTML Assembler: Chapter 13: Writing relocatable modules >ASMPC.HTML Assembler: Chapter 14: Interworking assembler with C >NEWFEATS.HTML Assembler: Appendix A: Changes to the assembler >ERRORS.HTML Assembler: Appendix B: Error messages >ASMEG.HTML Assembler: Appendix C: Example assembler fragments >WARNINGS.HTML Assembler: Appendix D: Warnings on the use of ARM assembler >AASM.HTML Assembler: Appendix E: Support for AAsm source :INTRO.HTML Assembler: Chapter 1: Introduction 1 idx-207 Introduction 5 idx-208 Installation 4 idx-209 Assembler tools 5 idx-210 Objasm 4 idx-211 This user guide 5 idx-212 Note on program examples 4 marker-54168 Conventions used in this manual :OBJASM.HTML Assembler: Chapter 2: ObjAsm 1 marker-514819 ObjAsm 4 idx-216 Starting ObjAsm 4 idx-217 The SetUp dialogue box 5 65408 Include 5 idx-218 Options 4 idx-219 The SetUp menu 5 idx-220 The command line 5 83455 Controlling syntax 5 marker-515135 Predefining a variable 5 marker-515147 Controlling cacheing 5 idx-221 Handling warnings and errors 5 12875 Listings 5 marker-515198 Choosing your work directory 5 marker-515203 Specifying other command line options 4 marker-515224 ObjAsm output 4 marker-515235 ObjAsm icon bar menu 4 idx-222 Example ObjAsm session 4 marker-515249 ObjAsm command lines 5 ObjAsm Command line options available from the desktop 5 92739 Command line options not available from the desktop :CPU.HTML Assembler: Chapter 3: The ARM CPU 1 marker-75869 The ARM CPU 4 idx-25 Introduction 5 idx-26 Bus widths 5 idx-27 Instruction set 5 idx-28 Pipelining 5 idx-29 Memory interface 5 idx-30 Data types 4 marker-75904 Block diagram of core 4 18456 26 bit architecture 5 62416 Processor modes 5 59579 Registers 5 67780 Register R15 5 18312 Register R14 5 marker-76472 Changing operating modes 4 45809 32 bit architecture 5 idx-31 New features in ARM6 5 idx-32 Processor configuration 5 idx-33 Processor modes 6 marker-76109 The 26 bit processor modes 5 idx-34 RISC OS processor configuration and modes 5 90965 Registers 5 39194 The CPSR and SPSR registers 4 marker-76204 Exceptions 5 idx-35 Introduction 5 96092 FIQ (Fast interrupt request) 5 idx-36 IRQ (Interrupt request) 5 94967 Address exception trap 5 idx-37 Abort 6 marker-76292 Abort during instruction prefetch 6 marker-76350 Abort during data access 6 idx-38 Abort during an internal cycle 6 idx-39 Using aborts to implement virtual memory systems 5 marker-76370 Software interrupt 5 idx-40 Undefined instruction trap 5 idx-41 Reset 5 idx-42 Vector summary 5 idx-43 Exception Priorities 5 idx-44 Interrupt latencies :ASMLANG.HTML Assembler: Chapter 4: ARM assembly language 1 84484 ARM assembly language 4 idx-16 General 4 idx-17 Input lines 4 marker-804592 AREAs 5 81755 Area attributes 4 marker-804646 ORG and ABS 4 marker-804660 Symbols 4 marker-804729 Labels 4 marker-804731 Local labels 5 idx-18 References to local labels 4 marker-804740 Comments 4 marker-804741 Constants 5 marker-804742 Numbers 5 marker-804743 Strings 5 marker-804744 Boolean 4 idx-19 The END directive :INSTRSET.HTML Assembler: Chapter 5: CPU instruction set 1 17921 CPU instruction set 4 marker-867132 The condition field 5 idx-71 Conditional instruction sequence 4 idx-72 Instruction timings 4 marker-867161 The barrel shifter 5 idx-73 Unshifted register 5 idx-74 Register shifted by a constant amount 5 idx-75 Value resulting from rotating register and carry bit one bit right 5 idx-76 Register shifted by n bits 5 idx-77 8-bit constant rotated right by 2n bits 5 idx-78 8-bit constant rotated right by 2n bits and specified explicitly 4 marker-867233 Shift types 5 idx-79 Mnemonics 5 marker-867281 Specification of the shift amount 6 idx-80 Instruction specified shift amount 6 idx-81 Register specified shift amount 5 marker-867313 Logical shift left, or arithmetic shift left 6 idx-82 Special cases 5 marker-867314 Logical shift right 6 idx-83 Special cases 5 marker-846603 Arithmetic shift right 6 idx-84 Special cases 5 marker-846604 Rotate right 6 idx-85 Special cases 5 marker-857753 Rotate right with extend 4 idx-86 Coprocessor instructions 2 marker-867339 Branch, Branch with Link (B, BL) 5 idx-87 Instruction format 5 idx-88 Assembler syntax 5 idx-89 Synopsis 5 94385 The link bit 5 idx-90 32 bit operation 6 idx-91 Calculating the offset 6 idx-92 The link bit 5 idx-93 Examples 2 39219 Data processing 5 idx-94 Instruction format 5 idx-95 Assembler syntax 6 idx-96 MOV and MVN - single operand 6 idx-97 CMN, CMP, TEQ and TST - no result written 6 idx-98 ADC, ADD, AND, BIC, OR, ORR, RSB, RSC, SBC, SUB - two operands 6 idx-99 Parameters 6 60135 Opcodes 5 idx-100 Synopsis 5 62074 The S bit 6 idx-101 Logical operations (AND, BIC, EOR, MOV, MVN, ORR, TEQ, TST) 6 idx-102 Arithmetic operations (ADC, ADD, CMP, CMN, RSB, RSC, SBC, SUB) 5 idx-103 The P flag 5 marker-867497 Shifts 5 marker-867498 Immediate operand rotates 5 marker-867505 Using R15 as the destination or operand 6 27425 Using R15 as the destination 6 14951 Using R15 as an operand 5 idx-104 32 bit operation 6 idx-105 TEQP, TSTP, CMPP and CMNP 6 idx-106 Using R15 as the shift register 6 idx-107 Using R15 as the destination 5 idx-108 Examples 2 marker-867520 PSR transfer (MRS, MSR) 5 idx-109 Instruction format 5 idx-110 Assembler syntax 5 idx-111 Synopsis 5 idx-112 Operand restrictions 5 idx-113 Reserved bits 5 idx-114 Examples 2 marker-867605 Multiply and Multiply-Accumulate (MUL, MLA) 5 idx-115 Instruction format 5 idx-116 Assembler syntax 5 idx-117 Synopsis 5 idx-118 PSR flags 5 idx-119 Operand restrictions 5 idx-120 32 bit operation 5 idx-121 Examples 2 marker-867632 Multiply Long and Multiply-Accumulate Long (UMULL, SMULL, UMLAL, SMLAL) 5 idx-122 Instruction format 5 idx-123 Assembler syntax 5 idx-124 Synopsis 5 idx-125 PSR flags 5 idx-126 Operand restrictions 5 idx-127 Examples 2 marker-867651 Single data transfer (LDR, STR) 5 idx-128 Instruction format 5 idx-129 Assembler syntax 5 idx-130 Synopsis 5 idx-131 Offsets and auto-indexing 5 idx-132 Shifted register offset 5 idx-133 Bytes and words 5 marker-867689 Use of R15 5 marker-867690 Address exceptions 5 marker-867691 Data Aborts 5 idx-134 32 bit operation 5 idx-135 Examples 2 marker-867705 Block data transfer (LDM, STM) 5 idx-136 Instruction format 5 idx-137 Assembler syntax 6 idx-138 Addressing mode names 5 idx-139 Synopsis 5 idx-140 The register list 5 idx-141 Addressing modes 5 idx-142 Transfer of R15 5 marker-867749 Forcing transfer of the user bank 5 idx-143 Use of R15 as the base 5 idx-144 Inclusion of the base in the register list 5 idx-145 When the base register is in the list of registers 5 marker-867751 Address exceptions 5 marker-867752 Data Aborts 6 idx-146 Aborts during STM instructions 6 idx-147 Aborts during LDM instructions 5 idx-148 32 bit operation 5 idx-149 Examples 2 marker-867776 Single data swap (SWP) 5 idx-150 Instruction format 5 idx-151 Assembler syntax 5 idx-152 Synopsis 5 idx-153 Bytes and words 5 idx-154 Use of R15 5 marker-867787 Data aborts 5 idx-155 Examples 2 marker-867804 Software interrupt (SWI) 5 idx-156 Instruction format 5 idx-157 Assembler syntax 5 idx-158 Synopsis 5 idx-159 Return from the supervisor 5 idx-160 Comment field 5 idx-161 32 bit operation 5 idx-162 Examples 2 marker-867817 Coprocessor data operations (CDP) 5 idx-163 Instruction format 5 idx-164 Assembler syntax 5 idx-165 Synopsis 5 idx-166 The coprocessor fields 5 idx-167 Restriction 5 idx-168 Examples 2 marker-867871 Coprocessor data transfers (LDC, STC) 5 idx-169 Instruction format 5 idx-170 Assembler syntax 5 idx-171 Synopsis 5 idx-172 The coprocessor fields 5 idx-173 Addressing modes 5 idx-174 Address alignment 5 idx-175 Use of R15 5 idx-176 Address exceptions 5 marker-867879 Data aborts 5 idx-177 32 bit operation 5 idx-178 Examples 2 marker-867892 Coprocessor register transfers (MCR, MRC) 5 idx-179 Instruction format 5 idx-180 Assembler syntax 5 idx-181 Synopsis 5 idx-182 The coprocessor fields 5 marker-867898 Transfers to R15 5 idx-183 Transfers from R15 5 idx-184 32 bit operation 6 idx-185 Transfers to R15 6 idx-186 Transfers from R15 5 idx-187 Examples 2 33017 Undefined instructions 5 idx-188 Instruction format 5 idx-189 Assembler syntax 5 idx-190 Synopsis 2 idx-191 Instruction set summary 5 idx-192 Instruction formats 5 idx-193 Assembler syntax 6 idx-194 Parameters for the above, alphabetically sorted 5 idx-195 Synopsis 2 marker-867930 Further instructions 4 idx-196 Extended range immediate constants 5 idx-197 Synopsis 4 marker-846828 The ADR instruction 5 idx-198 Assembler syntax 5 idx-199 Synopsis 6 idx-200 Register-relative 6 idx-201 Program-relative 6 idx-202 Numeric 4 marker-867956 The ADRL instruction 5 idx-203 Assembler syntax 5 idx-204 Synopsis 4 marker-867966 Literals 5 idx-205 Assembler syntax 5 idx-206 Synopsis :FPINSTRS.HTML Assembler: Chapter 6: Floating point instructions 1 marker-218226 Floating point instructions 4 idx-46 Programmer's model 4 idx-47 Available systems 4 idx-48 Precision 4 97842 Floating point number formats 5 marker-216065 IEEE Single Precision (S) 5 marker-216099 IEEE Double Precision (D) 5 marker-216140 Double Extended Precision (E) 5 marker-216194 Packed Decimal (P) 5 marker-216292 Expanded Packed Decimal (EP) 4 idx-49 Floating point status register 5 idx-50 System ID byte 5 idx-51 Exception Trap Enable Byte 5 idx-52 System Control Byte 6 idx-53 ND - No denormalised numbers bit 6 idx-54 NE - NaN exception bit 6 idx-55 SO - Select synchronous operation of FPA 6 idx-56 EP - Use expanded packed decimal format 6 idx-57 AC - Use alternative definition for C flag on compare operations 5 92907 Cumulative Exception Flags Byte 6 idx-58 IVO - invalid operation 6 idx-59 DVZ - division by zero 6 idx-60 OFL - overflow 6 idx-61 UFL - underflow 6 idx-62 INX - inexact 4 idx-63 Floating Point Control Register 5 idx-64 The FPPC system 5 idx-65 The FPA system 4 idx-66 Assembler directives and syntax 5 51849 Floating point number input 5 idx-67 NOFP directive 5 idx-68 Floating point register equating: FN 5 marker-216842 Floating point store loading directives 4 idx-69 The instruction set 5 marker-217981 Floating point coprocessor data transfer 6 86737 Floating point literals 5 marker-218023 Floating point coprocessor multiple data transfer 5 marker-218047 Floating point coprocessor register transfer 5 marker-218108 Floating point coprocessor data operations 5 marker-218181 Floating point coprocessor status transfer 4 idx-70 Finding out more... :DIRECTIV.HTML Assembler: Chapter 7: Directives 1 marker-804938 Directives 4 marker-804976 Storage reservation and initialisation - DCB, DCW and DCD 4 marker-804964 Floating point store initialisation - DCFS and DCFD 4 marker-804980 Describing the layout of store - ^ and # 4 marker-805004 Organisational directives - END, ORG, LTORG and KEEP 4 marker-805011 Links to other object files - IMPORT and EXPORT 4 marker-805024 Links to other source files - GET/INCLUDE 4 marker-805026 Diagnostic generation - ASSERT and ! 4 marker-805028 Dynamic listing options - OPT 4 marker-805033 Titles - TTL and SUBT 4 marker-805038 Miscellaneous directives - ALIGN, NOFP, RLIST and ENTRY :SYMBOLIC.HTML Assembler: Chapter 8: Symbolic capabilities 1 idx-223 Symbolic capabilities 4 idx-224 Setting constants 4 marker-804723 Local and global variables - GBL, LCL and SET 4 marker-804733 Variable substitution - $ 4 idx-225 Built-in variables :EXPROP.HTML Assembler: Chapter 9: Expressions and operators 1 marker-804680 Expressions and operators 4 marker-804732 Unary operators 4 marker-804738 Binary operators 5 marker-804785 Multiplicative operators 5 marker-804786 String manipulation operators 5 marker-804787 Shift operators 5 marker-804788 Addition and logical operators 5 marker-804789 Relational operators 5 marker-804790 Boolean operators :CONDASM.HTML Assembler: Chapter 10: Conditional assembly 1 marker-803541 Conditional and repetitive assembly 4 idx-20 Conditional assembly 5 idx-21 Simple use of the IF and ENDIF directives 2 idx-22 Simple use of the IF, ELSE and ENDIF directives 2 idx-23 Conditional assembly and the NoTerse option 2 idx-24 An example 1 marker-803658 Repetitive assembly :MACROS.HTML Assembler: Chapter 11: Macros 1 marker-803644 Macros 4 idx-213 Syntax 4 marker-803659 Local variables 4 marker-803662 MEXIT directive 4 idx-214 Default values 4 idx-215 Macro substitution method 4 marker-803686 Nesting macros 4 71146 A division macro :EXHANDLE.HTML Assembler: Chapter 12: Exception handling 1 marker-803255 Exception handling 4 42424 RISC OS processor configuration and modes 4 marker-803266 The pre-veneers 5 idx-45 Entering 32 bit modes 4 marker-803286 Claiming the hardware vectors 4 40353 Writing to the FIQ vector :WRITERM.HTML Assembler: Chapter 13: Writing relocatable modules 1 marker-803360 Writing relocatable modules in assembler 4 idx-243 Assembler directives 4 idx-244 Example :ASMPC.HTML Assembler: Chapter 14: Interworking assembler with C 1 marker-803733 Interworking assembler with C 4 idx-1 Examples 5 idx-2 PrintLib 6 30122 Compiling the CTestPrLib example 6 idx-3 Compiling and linking CTestPrLib in separate stages 5 marker-803753 CStatics :NEWFEATS.HTML Assembler: Appendix A: Changes to the assembler 1 marker-556595 Changes to the assembler :ERRORS.HTML Assembler: Appendix B: Error messages 1 marker-556616 Error messages :ASMEG.HTML Assembler: Appendix C: Example assembler fragments 1 marker-556760 Example assembler fragments 2 marker-556769 Using the conditional instructions 4 idx-4 Using conditionals for logical OR 4 idx-5 Absolute value 4 idx-6 Combining discrete and range tests 4 idx-7 Division and remainder 2 idx-8 Pseudo-random binary sequence generator 2 marker-556776 Multiplication by a constant 4 idx-9 Multiplication by 2n (1,2,4,8,16,32...) 4 idx-10 Multiplication by 2n+1 (3,5,9,17...) 4 idx-11 Multiplication by 2n-1 (3,7,15...) 4 idx-12 Multiplication by 6 4 idx-13 Multiply by 10 and add in extra number 4 idx-14 General recursive method for Rb := Ra×C, C a constant 2 idx-15 Loading a word from an unknown alignment 2 marker-556797 Sign/zero extension of a half word 2 marker-556799 Return setting condition codes 2 marker-556792 Full multiply :WARNINGS.HTML Assembler: Appendix D: Warnings on the use of ARM assembler 1 27297 Warnings on the use of ARM assembler 4 idx-226 Restrictions to the ARM instruction set 4 idx-227 Instructions and code sequences to avoid 5 marker-557392 TSTP/TEQP/CMPP/CMNP: Changing mode 5 idx-228 LDM/STM: Forcing transfer of the user bank (Part 1) 5 idx-229 LDM: Forcing transfer of the user bank (Part 2) 5 marker-557425 SWI/Undefined Instruction trap interaction 5 marker-557427 Undefined instruction/Prefetch abort trap interaction 5 idx-230 Single instructions to avoid 6 marker-557428 Any instruction that uses the 1111 condition code 6 idx-231 Data processing 6 idx-232 Multiply and multiply-accumulate 6 idx-233 Single data transfer 6 idx-234 Block data transfer 6 idx-235 Single data swap 6 idx-236 Coprocessor data transfers 6 idx-237 Undefined instructions 6 idx-238 Register access after an in-line mode change 6 marker-557443 Register access after an LDM that forces user mode data transfer 5 idx-239 Other points to note 6 marker-557444 Use of R15 6 marker-557450 STM: Inclusion of the base in the register list 6 marker-557452 MUL/MLA: Register restrictions 6 marker-557457 LDM/STM: Address Exceptions 6 marker-557456 LDC/STC: Address Exceptions 6 marker-557466 LDC: Data transfers to a coprocessor fetch more data than expected 4 idx-240 Static ARM problems 6 idx-241 Case 1: LDR Rd,[PC,#expression]! 6 idx-242 Case 2: LDR Rd,[PC],#expression :AASM.HTML Assembler: Appendix E: Support for AAsm source 1 marker-556608 Support for AAsm source 4 idx-0 The -ABSolute option =INSTRSET.HTML#marker-867339 Branch, Branch with Link (B, BL) =INSTRSET.HTML#39219 Data processing =INSTRSET.HTML#marker-867520 PSR transfer (MRS, MSR) =INSTRSET.HTML#marker-867605 Multiply and Multiply-Accumulate (MUL, MLA) =INSTRSET.HTML#marker-867632 Multiply Long and Multiply-Accumulate Long (UMULL, SMULL, UMLAL, SMLAL) =INSTRSET.HTML#marker-867651 Single data transfer (LDR, STR) =INSTRSET.HTML#marker-867705 Block data transfer (LDM, STM) =INSTRSET.HTML#marker-867776 Single data swap (SWP) =INSTRSET.HTML#marker-867804 Software interrupt (SWI) =INSTRSET.HTML#marker-867817 Coprocessor data operations (CDP) =INSTRSET.HTML#marker-867871 Coprocessor data transfers (LDC, STC) =INSTRSET.HTML#marker-867892 Coprocessor register transfers (MCR, MRC) =INSTRSET.HTML#33017 Undefined instructions =INSTRSET.HTML#idx-191 Instruction set summary =INSTRSET.HTML#marker-867930 Further instructions